#!/usr/bin/env bash
#-------------------------------------------------------
#	FileName	: miverilog.sh
#	Author		：hpy
#	Date		：2021年05月17日
#	Description	：
#-------------------------------------------------------

#cd $(dirname $0)

function main(	) {
	#compAll
	case $1 in 
		-h) mhelp ;; 
		-i) minit ;;  
		-r) compAll ;;
		*) mhelp ;; 
	esac 
}

function mhelp () {
cat<<EOF
	Usage:$(basename $0) <param> 
		-h 	help
		-i 	init project,make tb.v 
		-r	run iverilog but don't open gtkwave!'
EOF

}
function pre() {
	test ! -d sim && mkdir sim
	rm -rf sim/*
	
}
function compAll(){
	pre 
	local src=$(find -name "*.v")
	iverilog -o sim/wave $src 
	cd sim 
	#echo "------------- start -------------"
	vvp wave | awk 'NR>2{print $0}'

}

function mkTb() {
	test -f tb.v && echo "exist tb.v" && exit 0 
cat<<EOF > tb.v 
\`timescale 1ns / 1ps
module tb ;
reg clk,rst_n;

//生成始时钟
parameter NCLK = 2;
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 

/****************** BEGIN ADD module inst ******************/
//Modulenamme top (rst_n,clk);
/****************** BEGIN END module inst ******************/

initial begin
    \$dumpfile("wave.lxt2");
    \$dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end

initial begin
   	rst_n = 1;
    	#(NCLK) rst_n=0;
    	#(NCLK) rst_n=1; //复位信号

	repeat(100) @(posedge clk)begin

	end 
	\$dumpflush;
	\$finish;
	\$stop;	
end
initial begin 	
	\$monitor("%d %b",\$time,clk) ; 
end 
endmodule
EOF
	echo "make tb.v success!"
}

function minit(	){
	mkTb 
}
#---------------------------------
main $* 


